Functional verification systems, including hardware emulation systems and simulation acceleration systems, utilize interconnected programmable logic chips or interconnected processor chips. Examples of systems using programmable logic devices are disclosed in, for example, U.S. Pat. No. 6,009,256 entitled “Simulation Emulation System and Method,” U.S. Pat. No. 5,109,353 entitled “Apparatus for emulation of electronic hardware system.” U.S. Pat. No. 5,036,473 entitled “Method of using electronically reconfigurable logic circuits,” U.S. Pat. No. 5,475,830 entitled “Structure and method for providing a reconfigurable emulation circuit without hold time violations,” and U.S. Pat. No. 5,960,191 entitled “Emulation system with time-multiplexed interconnect.” U.S. Pat. Nos. 6,009,256, 5,109,353, 5,036,473, 5,475,830, and 5,960,191 are incorporated herein by reference. Examples of hardware logic emulation systems using processor chips are disclosed in, for example, U.S. Pat. No. 6,618,698 “Clustered processors in an emulation engine,” U.S. Pat. No. 5,551,013 entitled “Multiprocessor for hardware emulation,” U.S. Pat. No. 6,035,117 entitled “Tightly coupled emulation processors,” U.S. Pat. No. 6,051,030 entitled “Emulation module having planar array organization,” and U.S. Pat. No. 7,739,093 entitled “Method of visualization in processor based emulation system.” U.S. Pat. Nos. 6,618,698, 5,551,013, 6,035,117, 6,051,030, and 7,739,093 are incorporated herein by reference.
Functional verification systems help to shorten the time it takes to design a customized application specific integrated circuits (ASICs) by allowing designers to emulate the functionality of the ASIC before a production run of the ASIC has begun. Functional verification systems help to ensure ASICs are designed correctly the first time, before a final product is produced.
A particular processor-based hardware functional verification system (sometimes referred to as an “emulator,” “emulation system,” or the like) may contain numerous emulation chips that transmit data between one another. A serializer/deserializer (SerDes) is typically used to allow a large amount of data to transmit between chips, while minimizing the number of input/output (I/O) pins and interconnects needed by converting data between parallel interconnections within the chip to a serial signal transmitted on the interconnection between chips in each direction. The receiving chip then converts the serial interconnection back into a parallel interconnection.
The serial interconnect may encode the data to be transmitted. Encoding involves transforming the data bits to be transmitted into a new set of bits (or characters) to be transmitted. The number of encoded bits or characters is generally greater than the number of original data bits for a given word. Such encoding may be desired to reduce the DC component, also known as disparity or bias, of the transmitted signal, or add or modify bits for various transmission purposes, including synchronization, clock recovery, word alignment, error correction, error mitigation, tracking, or routing.
One encoding technique is known as 8B/10B as described for example in U.S. Pat. No. 4,486,739, which is hereby incorporated by reference in its entirety. 8B/10B is typically a line code where each eight-bit data byte is converted to a 10-bit transmission character to achieve DC-balance and bounded disparity, while providing enough state changes to allow for reasonable clock recovery.
Although the present methods of encoding are useful to a degree, there still exists a need in the field for reduced latency, reduced error, and conservative serial streams. Thus, for at least these reasons there is a need for an improved method and system for encoding by a serializer/deserializer of an emulation chip of a hardware functional verification system.